Memory-efficient, multithreaded engines utilize available server cores to speed up automatic test pattern generation (ATPG) and silicon diagnosis Twenty-five percent fewer test patterns reduce test ...

Today's chip designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries, and gate counts are pushing towards the 100M gate mark. Semiconductor companies creating these ...

New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests. Automatic test pattern generation (ATPG) tools perform ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

TetraMAX II ATPG reduced test generation runtime by an order of magnitude, from an overnight run to less than one hour, while producing 50 percent fewer patterns DecaWave met their silicon test time ...

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test ...

The current shift in the test methodologies is away from the ubiquitous single stuck-at fault model. The best test for any device is to exhaustively test the device. The quality of such a test would ...

Today’s huge, deep submicron system on chip (SoC) designs present many challenges at every stage of development, from architectural exploration to volume production. This post addresses the specific ...